Mobile communication devices such as cellular telephones, personal digital assistants (PDAs), and handheld devices are now required to perform more sophisticated communication functions, as well as time management functions. Although some of these communication functions and time management function have been tightly integrated into single chip solutions such as a system-on-chip (SoC), thereby resulting in significantly reduced form factors, power consumption requirements still remain a cause for concern. In general, the greater the number of transistors or devices with transistors that are utilized within an integrated circuit (IC), the greater the number of amount of power or electrical energy that is consumed. Although a large amount of electrical power or energy is consumed by transistors within an integrated circuit (IC), an even larger amount of power is consumed by the wires that route clock signals, because clock signals are constantly switching. Therefore extensive clock gating is often used to confine the wires that load the clock network.
FIG. 1 is a block diagram of a conventional integrated circuit design illustrating a clock tree. Referring to FIG. 1, there is shown a phase lock loop (PLL) 102, gate control block 134, devices D1, D2, D3, D4, D5, D6, D7 referenced as 104, 106, 108, 110, 112, 114, 136 respectively, and gates G1, G2, G3, G4, G5, G6, G7, G8, G9 referenced as 116, 118, 120, 122, 124, 126, 128, 130, 132, respectively.
In operation, the gate control block 134 controls gates (G1-G9) 116, 118, 120, 122, 124, 126, 128, 130, 132. If the gate G1 116 is ON, then a clock signal generated by the PLL 102 passes to gates G2 118, G6 126 and G9 132. In this regard, gate G1 116 may be regarded as the main gate. While gate G1 116 is ON, gate G2 118 is ON, then the clock signal generated by the PLL 102 passes to gates G3 124, G4 122, and G5 124. If gate G3 120 is ON, then the clock signal passes to device D1 104. If gate G4 122 is ON, then the clock signal passes to device D2 106. If gate G5 124 is ON, then the clock signal passes to device D3 104. If any of gates G3 120, G4 122 and G5 124 is OFF, then the device coupled to the corresponding gate will not receive the clock signal generated by PLL 102. For example, if gate G4 122 is off then device D2 106 will not receive the clock signal generated by PLL 102.
If the gate G1 116 is ON and gate G6 126 is ON, then the clock signal generated by the PLL 102 passes to gates G7 128 and G8 130. If gate G7 128 is ON, then the clock signal passes to device D4 110. If gate G8 130 is ON, then the clock signal passes to device D5 112. If any of gates G7 128, and G8 130 is OFF, then the device coupled to the corresponding gate will not receive the clock signal generated by PLL 102. For example, if gate G8 130 is off then device D5 112 will not receive the clock signal generated by PLL 102.
A major drawback with the conventional clock tree illustrated in FIG. 1 is that the gate control block 134 and gates G1-G9 116-132 are configured when the integrated circuit is fabricated and a customer, based on a specific circuit design, does not have the flexibility to disable or enable certain clocks when the customer has application scenarios that are not covered in the design phase. A device, which is never utilized in the customer application can still receive clock signals from the PLL 102, consumes precious and limited power resources. For example, if gates G1 and G2 are both ON, then the clock signal generated by the PLL 102 passes to gates G3, G4 and G5. However, there may be instances where gate G4 is ON and device D2 106 is consuming power even thought it is never in use in the customer application. In another example, if gates G1 and G6 are both ON, then the clock signal generated by the PLL 102 passes to gates G7 and G8. However, there may be instances where gate G8 should be ON at situations different from what configured in the gate control block 134 because the customer uses device D5 112 in a way different from what the integrated circuit designer anticipated.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.